ADC12DJxx00 - ADC12DJ3200

ADC12DJ3200 (正在供货)

ADC12DJxx00

 

Sample Availability

Prototype samples are available (PADC12DJ3200AAV). Order Now

描述

ADC12DJ3200 is an RF-sampling giga-sample ADC that can directly sample input frequencies from DC to above 10 GHz. In dual channel mode, ADC12DJ3200 can sample up to 3200-MSPS and in single channel mode up to 6400-MSPS. Programmable tradeoffs in channel count (dual channel mode) and Nyquist bandwidth (single channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full power input bandwidth (-3 dB) of 8.0 GHz, with usable frequencies exceeding the -3 dB point in both dual and single channel modes, allows direct RF sampling of L-band, S-band, C-band and X-band for frequency agile systems.ADC12DJ3200 uses a high speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications. Optional digital down converters (DDCs) in dual channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).

特性

  • ADC Core:
    • 12-bit Resolution
    • Up to 6.4 GSPS in single channel mode
    • Up to 3.2 GSPS in dual channel mode
  • Buffered Analog Inputs with VCMI of 0 V
    • Analog input bandwidth (-3 dB): 8.0 GHz
    • Usable input frequency range: >10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
  • Noise Floor (No signal, VFS = 1.0 VPP):
    • Dual channel mode: -151.8 dBFS/Hz
    • Single channel mode: -154.6 dBFS/Hz
  • Noiseless Aperture Delay (TAD) Adjustment
    • Precise sampling control: 19-fs step
    • Temperature and voltage invariant delays
  • Easy-to-use Synchronization Features
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B Serial Data Interface
    • Supports subclass 0 and 1
    • Maximum lane rate: 12.8 Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital Down-Converters in Dual Channel Mode
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x or 16x decimation
    • Four independent 32-bit NCOs per DDC
  • Power consumption: 3.0 W
  • Power Supplies: 1.1 V, 1.9 V
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参数 与其它产品相比 高速 ADCs (>10MSPS)

 
Resolution (Bits)
Sample Rate (Max) (MSPS)
# Input Channels
SNR (dB)
ENOB (Bits)
SFDR (dB)
Power Consumption (Typ) (mW)
Input Range (Vp-p)
Interface
Operating Temperature Range (C)
Analog Input BW (MHz)
Input Buffer
Package Group
Package Size: mm2:W x L (PKG)
Rating
SINAD (dB)
Architecture
DNL (Typ) (+/-LSB)
INL (Typ) (+/-LSB)
Reference Mode
ADC12DJ3200
12   
3200
6400   
2
1   
56.6   
9   
67   
3000   
0.8   
JESD204B   
-40 to 85   
8000   
Yes   
FCBGA   
See datasheet (FCBGA)   
Catalog   
56   
Folding Interpolating   
0.3   
2.5   
Int